Simulating Drain Lag of GaN HEMTs with physics-based ASM model
P. Beleniotis1, F. Schnieder2, M. Rudolph1,2
Published in:
Proc. 15th European Microwave Integrated Circuits Conference (EuMIC 2020), Utrecht, Netherlands, Jan. 11-12, pp. 165-168 (2021).
Abstract:
This paper presents a drain-lag model for GaN HEMTs, enhancing the simulation accuracy of the physics-based compact model ASM-HEMT. The proposed trap model requires a minimum number of measurements and simplifies the extraction procedure by focusing only on intrinsic device related parameters. It is shown that this drain-lag description allows for highly accurate simulation of pulsed I-V output curves for the whole range of gate voltage, providing high modeling accuracy of transistor large-signal behavior without adding complexity to the existing model.
1 Brandenburg University of Technology Cottbus-Senftenberg (BTU), Ulrich L. Rohde Chair of RF and Microwave Techniques, Siemens-Halske-Ring 14, 03046 Cottbus, Germany
2 Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik, Gustav-Kirchhoff-Str. 4, 12489 Berlin, Germany
Keywords:
GaN HEMT modeling, compact model, ASM-HEMT, trapping effects, drain lag.
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