C. Kuring¹, M. Wolf², X. Geng¹, O. Hilt², J. Böcker¹, N. Wieczorek¹, J. Würfl² and S. Dieckerhoff¹

Published in:

11th International Conference on Integrated Power Electronics Systems (CIPS 2020), Berlin, Germany, Mar. 24-26, ETG-Fb. 161: CIPS 2020, ISBN 978-3-8007-5225-6, pp. 8-13 (2020).

Abstract:

Power electronic systems employing wide-bandgap GaN transistors promise high efficiency operation and superior power density but require minimized parasitic circuit elements and an effective cooling concept. This paper presents a halfbridge module integrating two GaN HEMTs with their gate drive stages and the DC-link capacitance on a multilayer AlN substrate. The small layer distance of 10 µm achieved on the GaN half-bridge module allows for minimization of layout related parasitic inductances. The parasitic circuit elements are evaluated and compared to conventional 4-layer PCB design using 3D-FEM field simulation and measurements. Due to a lateral commutation loop design, the GaN half-bridge module achieves notably lower parasitic capacitances but also a smaller commutation loop inductance. The thermal characterization of the fabricated half-bridge module validates the high cooling capability introduced by the AlN-substrate. The switching characteristics of the proposed GaN half-bridge module are studied in hard-switched mode.

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